1. Field of the Invention
The present invention relates generally to video signal processing apparatus and, more particularly, is directed to a video signal processing apparatus adapted for incorporation in a home video camera.
2. Description of the Prior Art
In a known home video camera, a binary value signal, for example, representing characters, indicia and the like to be used in creating a title, is generated in advance and converted into a color signal which is mixed or composed with a real moving picture video signal so as to provide a composite signal that may be displayed as a title picture. In such known home video camera, it is desirable to be able to mix other video signals as well as the generated binary value signal with the real moving picture video signal.
Further, it has been proposed to reduce noise in a video signal by using a so-called field memory, for example, as disclosed in Japanese Patent Published Gazette No. 62-3639. An example of a previously-proposed noise reducing circuit employing a field memory is shown in FIG. 1 in which a video signal Y applied to an input terminal 1 is supplied directly therefrom to an adder 2 having its output signal Y' supplied to an output terminal 3 and also to a field memory 4. Further, a video signal Y.sub.D delayed, for example, one field period, by the field memory 4, is supplied from the latter to one input of a subtractor 5 which, at its other input receives the video signal Y applied to the input terminal 1. Thus, the video signal Y applied to the input terminal 1 is subtracted from the delayed video signal Y.sub.D, and the result of such subtraction, that is, (Y.sub.D -Y), is supplied to a coefficient generator 6. The coefficient generator 6 provides, as its output, a signal k (Y.sub.D -Y) in which k is a coefficient provided in the generator 6 and which is selected in response to the magnitude of the difference or output (Y.sub.D -Y) from the 10 subtractor 5. Such output k (Y.sub.D -Y) from the coefficient generator 6 is applied to another input of the adder 2 so that the signal Y' appearing at the output of the adder 2, and hence derived at the output terminal 3, is expressed by the following noise reducing equation: EQU Y'=Y+k (Y.sub.D -Y)
or EQU Y'=(1-k)Y+kY.sub.D ( 1)
Therefore, noise can be reduced by properly selecting the value of the coefficient k in response to the magnitude of the difference (Y.sub.D -Y) between the signal Y at the input and the delayed signal Y.sub.D. More specifically, the value of the coefficient k is selected so as to provide a characteristic substantially as shown on FIG. 2, in which the inclination of the illustrated curve represents the coefficient k. In the characteristic curve shown on FIG. 2, the portion corresponding to a relatively large magnitude of the difference (Y.sub.D -Y) corresponds to a real moving picture and, accordingly, the value of the coefficient k is decreased. On the other hand, a portion of the curve or graph shown on FIG. 2 for a relatively small magnitude of the difference (Y.sub.D -Y) corresponds to a still picture and, accordingly, the coefficient k is then selected to be near 1.0, with the result that the amount of feedback through the field memory 4 is increased for reducing the noise in the output video signal.
In a practical embodiment of the coefficient generator 6, the latter may include, for example, a read only memory (ROM) from which there are derived output data k(Y.sub.D -Y) in response to the application to the ROM of the value (Y.sub.D -Y) as address data therefor. Further, in order to provide for varying the degree of noise reduction, the ROM may have a plurality of data patterns established therein which are selectively addressed.
It will be appreciated that, in the prior art noise reducing circuit described above with reference to FIG. 1, the field memory 4 thereof is used to mix video signals. If a so-called video image memory is employed as the field memory 4, such video image memory is generally arranged to generate data of a lower address from the inside of the memory in order to facilitate generation of address data at the outside of the memory, with data being written and/or read in units of, for example, 60 blocks. For the foregoing reason, if a so-called video image memory is used to mix the video signals in the noise reducing circuit, the signal cannot be readily rewritten in pixel units so that the video signals cannot be conveniently mixed.